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sw-block/design: mini-plan §11.7 — pillar 2/3 landed-SHA + test-name table

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Annotates pillar 2 (dual-line execution) and pillar 3 (receiver
convergence) rows with the landed commits + concrete test names so
the design narrative tracks the code:

  Pillar 2 — assembled-stack fault-injection
    7d051e2 — C3 fault-injection (recovery-package layer, spy sink):
              TestC3FaultInjection_BaseError_WalExitsViaCtx
              TestC3FaultInjection_OuterCancel_BothLanesWindDown
              TestC3FaultInjection_WalError_RunTerminates_NarrowVariantA
    9f62ebe — Pillar 2 fault-injection on the assembled stack
              (BlockExecutor + RecoverySink + Sender + WalShipper):
              TestPillar2A_BaseError_AssembledStack_FailReason
              TestPillar2B_LiveWrites_HighPressure_BarrierIntegrity
              TestPillar2C_WireAbortMidSession_AssembledStack_RestoresEmitContext

  Pillar 3 — receiver convergence under same-LBA conflict
    291e652 — slice-1: same-LBA arbitration on transport stack
    3495a12 — slice-1 polish (AchievedLSN assertion, replica==primary
              comparison, comment fixes, companion-SHA list)
              TestPillar3Slice1_ReceiverConvergence_LiveOverwritesBacklog_SameLBAs
              (transport-stack only; slice-2 lifts to engine path
               via dual_lane_engine_test.go)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
pingqiuandClaude Opus 4.7 committed 2026-04-30 11:51:20 -07:00
1 parent 822c588d08
commit 7dfb0172d1
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sw-block/design/v3-recovery-wal-shipper-mini-plan.md
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@@ -296,8 +296,8 @@ Choice — **per-connection format dispatch**, not single-format unification. Du
| Pillar | Must prove | Tests (extend / add) |
|--------|------------|---------------------|
| **1 — WalShipper: backlog vs incoming** | **`ModeBacklog`**: timer + **`DrainBacklog`** / **`ScanLBAs`**, **`NotifyAppend`** lag-only; **`ModeRealtime`**: **`NotifyAppend`** tail + **`StrictRealtimeOrdering`**; **§13** carve-out | `core/transport`: **`TestC2_*`**, **`TestWalShipper_*`**, **`replicaid_unified_test`**; add **assembled-path** sessions (real **`RecoverySink`**, not shipper-only) |
| **2 — Dual-line execution** | **BASE ∥ WAL** overlap, **`writeMu`**-bounded interleave; correct **profile / port**; **no corrupted frames** | **`TestC3_BaseWalParallel_FramesInterleave`**, dual-lane E2E; **item (2)**: **C3 ctx fault-injection** |
| **3 — Receiver recover convergence** | Replica accepts **interleaved base + WAL** on recover path, **bitmap / `checkMonotonic`**, **barrier `achievedLSN`**, moves toward **idle / healthy** | **`core/recovery` E2E**, **`dual_lane_engine_test`**, **`replication/component` cluster**; stress: **live writes during session**; **T2** when §IV closed |
| **2 — Dual-line execution** | **BASE ∥ WAL** overlap, **`writeMu`**-bounded interleave; correct **profile / port**; **no corrupted frames** | **`TestC3_BaseWalParallel_FramesInterleave`**, dual-lane E2E; **item (2)**: **C3 ctx fault-injection** (**`7d051e2`** — `TestC3FaultInjection_BaseError_WalExitsViaCtx` / `_OuterCancel_BothLanesWindDown` / `_WalError_RunTerminates_NarrowVariantA`); assembled-stack lift (**`9f62ebe`** — `TestPillar2A_BaseError_AssembledStack_FailReason` / `TestPillar2B_LiveWrites_HighPressure_BarrierIntegrity` / `TestPillar2C_WireAbortMidSession_AssembledStack_RestoresEmitContext`) |
| **3 — Receiver recover convergence** | Replica accepts **interleaved base + WAL** on recover path, **bitmap / `checkMonotonic`**, **barrier `achievedLSN`**, moves toward **idle / healthy** | **`core/recovery` E2E**, **`dual_lane_engine_test`**, **`replication/component` cluster**; stress: **live writes during session**; **T2** when §IV closed. **Slice-1 landed 2026-04-30** (**`291e652`** + polish **`3495a12`**) — `TestPillar3Slice1_ReceiverConvergence_LiveOverwritesBacklog_SameLBAs` (transport-stack only; **slice-2** lifts to engine-driven path via `dual_lane_engine_test.go`) |
**Order**: **(1)** Phase 0 **committed + §11.6 receipt (SHA)** → **(2)** fault-injection → **(3)** widen matrix → **hardware soak** (**T2 / T7**).